1. Field of the Invention
The present invention relates to a communication control circuit, and particularly to a communication control circuit including a physical layer driver circuit (PHY circuit) in compliance with the IEEE (Institute of Electrical and Electronic Engineers) Standard 1394.
2. Description of the Related Art
Recent years have seen the development of a variety of bus standards for personal computer peripheral devices as computer interfaces. These bus standards for personal computer peripheral device include USB (Universal Serial Bus) standards and high-performance serial bus standards pursuant to IEEE Standard 1394. IEEE Standard 1394 is a standard for a high-speed serial bus that was developed principally by Apple Computer, Inc. This standard specifies physical and electrical standards for cables and connectors for interconnecting a wide range of devices including home-appliances, and defines international standards relating to protocol for realizing peer-to-peer communication between a maximum of 63 nodes.
The layer configuration of an IEEE 1394 serial bus is composed of three layers: a transaction layer, a link layer (hereinbelow referred to as “LINK”), and a physical layer (hereinbelow referred to as “PHY”).
The transaction layer executes transaction processing for asynchronous communication between the application layer and the node of a communication partner.
The link layer receives asynchronous instructions or data from the transaction layer, or receives isochronous instructions or data from the application layer, divides the received data into packets and transfers the packets to the physical layer, and assembles packets received from the physical layer into data and transfers the data to an upper layer.
The role of the PHY is to convert the data that are transferred from the LINK in the form of packets to electrical signals of a communication format that is pursuant to IEEE Standard 1394 and transmit the packets to the node of the transmission destination, and to transfer communication received from other nodes to the application layer of the transmission destination through the LINK of interest, or to transfer (repeat) to another node of the transmission destination. For this purpose, the chief electrical functions of the PHY circuit is the transmission and reception of packets and also bus arbitration.
IEEE Standard 1394 includes not only the specifications of electrical signals, but also mechanical specifications for cables and connectors. PHY circuit has the function of physically connecting the port of a node of interest with the port of a transmission destination node by way of connectors and cables pursuant to these mechanical specifications, i.e., the function of mechanical interfacing between the node and connectors and cables in accordance with IEEE Standard 1394.
IEEE Standard 1394 specifies half-duplex operation as the communication mode. In this communication mode, only one port executes packet transmission on an IEEE 1394 serial bus.
This half-duplex communication mode is performed using differential signals (signals that are symmetric with respect to the ground potential) of data signals and differential signals of strobe signals, the strobe signals being created by inverting the odd numbered bits of data signals. This encoding method of strobe signals is referred to as the data-strobe encoding method.
According to this data-strobe encoding method, a continuously transmitting data signal can be detected even in a case in which a signal of the same logic level continues on the data line and thus the electric potential of the data line is fixed, because the strobe signal changes. When the data-strobe encoding method is adopted, clocks are reproduced by exclusive-OR processing of data and strobe signals. The use of these reproduced clocks eliminates the need for a complicated clock extraction circuit on the receiving side and can reduce the clock skew of received data. Further, differential signals are used in order to remove noises introduced in the bus.
Arbitration is a process for assigning the right or priority to use a serial bus to each port. The arbitration method adopted in an IEEE 1394 serial bus is a method that guarantees that only one port sends data, i.e., a method that guarantees half-duplex processing.
A PHY circuit can have a plurality of ports for transmitting and receiving packets. In a cable environment, the ports of each PHY circuit are interconnected one-to-one by cables.
Ports and cables are driven by a tristate differential-output line driver of a low-voltage current mode. This line driver generates differential outputs from input signals. Each of the component signals of a differential signal can take on three states, i.e., 0 1 and “Z.” In this case, “Z” signifies the idle state or a non-driven state.
A cable that conforms to IEEE Standard 1394 is a four-wire or a six-wire cable. FIG. 1 shows a sectional view of a six-wire cable 401 that conforms to IEEE Standard 1394. A four-wire cable is made up by two twisted-pair cables, i.e., twisted-pair A (Tpa) cable 403 and twisted-pair B (Tpb) cable 405. The six-wire cable 401 includes the above-described two twisted-pair cables 403 and 405 and two power-supply lines for supplying power 402 and 404.
FIG. 2 shows a port of a PHY circuit for driving a cable including cable drive block for driving twisted pair A (hereinbelow abbreviated as “TPA drive block”) and cable drive block for driving twisted pair B (hereinbelow abbreviated as “TPB drive block”). This cable-drive port is explained, for example, M. Inada, “Introduction to IEEE Standard 1394 ” Second Edition, Chapter 2 (Gijyutsu-Hyoron Co. Ltd.).
As its essential elements, TPA drive block 500 is provided with line driver (hereinbelow referred to as “driver”) 502, line receiver (hereinbelow referred to as “receiver”) 503, and arbitration comparators 504 and 505.
As its essential elements, TPB drive block 520 is also provided with driver 522, receiver 523, and arbitration comparators 524 and 525.
As shown in FIG. 2, ground terminal VG and the two sets of terminals, terminals TPA and TPA* of TPA drive block 500 and terminals TPB and TPB* of TPB drive block 520 constitute an interface between the PHY circuit and the cables. When connecting two nodes, terminals TPA and TPA* of the TPA drive block of a first node are connected to terminals TPB and TPB* of the TPB drive block of a second node; and terminals TPB and TPB* of the TPB drive block of the first node are connected to terminals TPA and TPA* of the TPA drive block of the second node.
This way of connection of the twisted pair cables is hereinafter referred to as “cross-connected”.
When enable signal Strb_Enable is active, driver 502 for transmitting strobe signals Strb_Tx supplies a differential signal made up of a noninverted output signal of the same phase as input signal Strb_Tx and an inverted output signal of the reverse phase to terminals TPA and TPA*. Similarly, when enable signal Data_Enable is active, driver 522 for transmitting data signal Data_Tx of the TPB drive block supplies a differential signal made up of a non-inverted output signal of the same phase as input signal Data_Tx and an inverted output signal of the reverse phase to terminals TPB and TPB*.
Receiver 503 for receiving data signal Data_RX of the TPA drive block 500 differential-detects data signal Data_RX that is received by way of terminals TPA and TPA*. Receiver 523 for receiving strobe signals Strb_RX of the TPB drive block 520 differential-detects strobe signal Strb_RX that is received by way of terminals TPB and TPB*.
Arbitration comparators (504 and 505) of the TPA drive block 500 and arbitration comparators (524 and 525) of the TPB drive block 520 are each made up by two differential amplifiers having differing transition threshold values and each detect the tristate logical values of the Tpa cables and Tpb cables. These detected values, Arb_a and Arb_b, are used as arbitration control signals for bus-arbitration.
The TPA drive block provides Tp Bias. Tp Bias is supplied by way of operational amplifier 501 of a voltage-follower connection, and is in turn supplied to the TPA wire and TPA* wire by way of resistors 509 and 510. Tp Bias is grounded (denoted by VG) at terminal 512 through smoothening capacitor 511.
Differential amplifier 506 serves as a speed signal detector and detects the reception speed of packets. The packet transmission speed is designated by a speed signal Speed_TX, which controls the output currents of constant-current supplies 531 and 532 provided between TPB cable and VG 535 in the transmission-side TPB drive block at the time of Data_Prefix before transmission of packets.
Speed signal Speed_TX causes a bias current to flow between the TPA and TPA* of the reception-side TPA drive block. Capacitor 533 and resistor 534 make up a smoothening circuit.
The bias current, which corresponds to speed signal Speed_TX, flows through serial resistors 507 and 508 of the TPA drive block of the reception node and generates a voltage between TPA and TPA*. This voltage is divided by resistors 507 and 508, and the divided voltage is detected by differential amplifier 506 by comparing the divided voltages with Tp Bias to produce reception speed signal Speed_RX.
Differential amplifier 526 of the transmission drive block TPB compares voltages that are generated by dividing the bias voltage of the TPB cables by means of resistors 527 and 528 with reference voltage 0.8 V and detects the connection state between the drive block of interest and the node of the communication partner.
In the case of asynchronous transmission, which is one mode of IEEE 1394 communication, the transmission PHY circuit adds, in response to the transmission request (Request) of the LINK, a transmission data prefix signal (TX_DATA_PREFIX) at the beginning of a packet data signal and a transmission data end signal (TX_DATA_END) at the end of the packet data signal, as arbitration signals.
TX_DATA_PREFIX indicates the transmission start, and TX_DATA_END indicates the transmission end in accordance with the IEEE 1394 Std.
FIG. 3 shows an example of a timing chart illustrating the packet data signals that flow during transmission. FIGS. 4 and 5 are correspondence charts between the line states and the transmission arbitration codes (transmission arbitration control signals) and reception arbitration codes (reception arbitration control signals) defined in the IEEE 1394 Standard. Of the arbitration control signals and line states represented in FIGS. 4 and 5, the following points are of key importance in the explanation hereinbelow.
Referring to FIG. 4, the transmission prefix signal TX-DATA-PREFIX (transmission prefix signals added to the data and strobe signals) is detected to be Arb_a=0 and Arb_b=1 by arbitration comparators in the TPA and TPB drive blocks, respectively, on the transmission side.
Arb_a=0 and Arb_b=1 detected by arbitration comparators of the transmission node are interpreted by the bus arbitration block of the same transmission node as a reception end signal RX-DATA-END (cf. FIG. 5) which causes the reception block of the transmission node to be deactivated.
In this way, simultaneous occurrence of transmission and reception in a PHY circuit can be avoided to realize the half-duplex operation.
It is to be noted that the same transmission prefix signal is detected to be Arb_a=1 and Arb_b=0 by arbitration comparators in the PHY circuit of a reception node, because TPA and TPB terminals of a transmission node are cross-connected to TPB and TPA terminals of the reception node. For this reason, the transmission prefix signal sent from the transmission node is received by the reception node as a reception prefix signal RX-DATA-PREFIX (cf. FIG. 5) which causes the reception block of the reception node to be activated.
Referring again to FIG. 3, the figure shows that logic 0 and logic 1 are prefixed to a transmission strobe signal and a transmission data signal, respectively, as an arbitration signal TX-DATA-PREFIX. The arbitration signal is detected by arbitration comparators in the TPA and TPB drive blocks, which issues arbitration control signals, Arb_a=0 and Arb_b=1. The arbitration control signals are interpreted as RX-DATA-END by the transmission PHY circuit to cause the reception block of the transmission PHY circuit to be deactivated.
In FIG. 3, logic 1 and logic 0 suffixed to transmission strobe signal Strb_Tx and transmission data signal Data_Tx, respectively, as arbitration signal TX_DATA_END are detected to be Arb_a=1 and Arb_b=0 by arbitration comparators of the transmission node. These arbitration control signals, Arb_a=1 and Arb_b=0, are interpreted by the transmission PHY circuit as RX_DATA_PREFIX which causes reception of packet data to be allowed. In this way, when transmission of packet data ends, reception of packet data is allowed.
FIG. 6 is a timing chart showing packet data signals in the reception node. Since the Tp (twisted-pair) terminals of both ends of a Tp cable are cross-connected as described hereinabove, the line state Arb_a=0 and Arb_b=1 of the transmission node is detected as line state Arb_a=1 and Arb_b=0 in the reception node. Accordingly, the reception PHY circuit judges the arbitration signal Arb_a=1 and Arb_b=0 as the reception data prefix signal, Rx_Data_PREFIX, that indicates the start of reception (refer to FIG. 5). As a result, the reception PHY circuit activates its reception block, and receives the packet data. In this way, the reception PHY circuit, when receiving TX_DATA_PREFIX, starts reception of the packet data signal transmitted from the transmission node.
The arbitration comparators of the reception PHY circuit, upon detecting TX_DATA_END suffixed to the transmitted packet data signal, provides outputs of Arb_a=0 and Arb_b=1, which are an arbitration signal indicating the end of the reception (cf. FIG. 5). Whereby, the reception node stop receiving the packet data signal.
While Arb_a=1 and Arb_b=0 indicate RX_DATA_PREFIX as a reception arbitration signal (cf. FIG. 5), they also indicate TX_DATA_END as a transmission arbitration signal (cf. FIG. 4).
Thus, the reception PHY circuit, upon receiving Arb_a=1 and Arb_b=0 from its arbitration comparators, controls its transmission block to block the transmission of a packet data signal, thereby preventing the simultaneous reception and transmission of packet data signals.
While Arb_a=0 and Arb_b=1 indicate RX_DATA_END as a reception arbitration signal (cf. FIG. 5), they also indicate TX_DATA_PREFIX as a transmission arbitration signal (cf. FIG. 4).
The reception PHY circuit, upon receiving Arb_a=0 and Arb b=1 suffixed to the received packet data, judges the arbitration signal to be TX_DATA_PREFIX.
Thus, when transmission packet data are present, execution of transmission is guaranteed as soon as the reception of packet data ends.
The entire PHY circuit is next explained with reference to the figures. FIG. 7 is a block diagram showing the overall PHY circuit.
Referring now to FIG. 7, PHY circuit 1100 is made up by: cable drive block 129, transmission block 115, reception block 120, bus arbitration block 119, LINK interface block 111, local clock generation circuit 105, parallel/serial converters (P/S circuits) 123 and 124, serial/parallel converter (S/P circuit) 125, and clock reproduction circuit 128.
LINK interface block 111 interfaces communication of packet data and arbitration between a LINK circuit (not shown in the figure) and PHY circuit 1100. Cable drive block 129 is made up by low-voltage and low-current circuits such as drivers 130, 134, receivers 131, 135, and arbitration comparators 132, 136.
Arbitration comparators (hereinbelow abbreviated as “Arb Comp”) 132 and 136 perform differential-detection of arbitration signals added at the beginning and end of packet data transmitted or received, and judge their logical level. Arb Comps 132 and 136 supply to bus arbitration block 119 the judgment results, i.e., Arb_a and Arb_b that represent the line states of the TPA cable and TPB cable, respectively.
Drivers 130, 134 transmit packet data, and receivers 131, 135 receive packet data.
Bus arbitration block 119 responds to arbitration requests from LINK interface block 111, manages and controls each port, and performs the reset and configuration of the bus pursuant to the IEEE Std 1394.
Reception block 120 takes in data transmitted from the bus and synchronizes the data to a synchronizing clock signal. The synchronization is performed by clock reproduction circuit 128 and FIFO 122. Clock reproduction circuit 128 includes Exclusive-OR gate 126 and frequency demultiplier (FD) 127. Exclusive-OR gate 126 receives reception data signal Data_Rx and reception strobe signal Strb_Rx and generates a clock signal that is synchronized with the reception signals. Frequency demultiplier 127 frequency-demultiplies the clock signal that was generated by Exclusive-OR gate 126 and supplies the frequency-demultiplied clock to FIFO 122. The frequency-demultiplied clock is hereinafter referred to as a reproduced clock signal.
Under the control of reception control circuit 121, FIFO 122 stores parallel reception data signal Data_Rx supplied by way of S/P 125 in synchronization with the reproduced clock signal. The read-out of data from FIFO 122 is performed in synchronization with the synchronizing clock supplied from local-clock generator circuit 105 under the control of reception control circuit 121. The clock skew between the received data and the synchronizing clock can thus be absorbed and received data can be synchronized with the synchronizing clocks. The received data that are read out from FIFO 122 are both sent through output buffer 108 to an upper layer circuit and applied to selector (SEL) of transmission block 115.
Transmission control circuit (Transmission CTRL CCT) 118 of transmission block 115 receives bus control signals from bus arbitration block 119, controls the output of drivers 130 and 134 in accordance with the instructions of the bus control signals, and controls the selection of SEL 116.
SEL 116 receives both packet data signal 101 provided by way of LINK interface block 111 and the received data that are read out from FIFO 122, and selects one of these inputs in accordance with a selection control signal. The output of SEL 116 is supplied to data-strobe encoding circuit 117. As will be explained hereinbelow with reference to FIG. 9, data-strobe encoding circuit 117 generates transmission strobe signal Strb_Tx based on data signals. Transmission strobe signal Strb_Tx is sent by way of P/S circuit 123 to driver 130. Data-strobe encoding circuit 117 also transmits packet data signals 101 received from the LINK or the received data that have been read out from FIFO 122 to driver 134 by way of P/S circuit 124 as transmission data signal Data_Tx. The arbitration signals, TX_DATA_PREFIX and TX_DATA_END, are added to both of the transmission strobe signal and the transmission data signal in Data-strobe encoding circuit 117.
The received data that have been read from FIFO 122 are repeated to another PHY circuit in case in which the received data are selected by SEL 116.
Explanation next concerns the operation of the PHY circuit shown in FIG. 7.
Transmission request 102 given from a LINK circuit (not shown) is taken in by buffer 114 of LINK interface block 111 and sent to bus arbitration block 119.
PHY circuit generates arbitration signal TX_DATA_PREFIX for transmitting data, and in a case in which the right or priority to use the bus has been obtained, takes packet data signal 101 in data-strobe encoding circuit 117 of transmission block 115 by way of buffer 109 and buffer 1113 of LINK interface block 111, and generates a strobe signal.
This data-strobe encoding circuit 117 inverts the odd-numbered bits of the data signals and generates strobe signals (refer to FIG. 9 and data-strobe encoding method).
The strobe signal, added with arbitration signals, i. e., TX DATA_PREFIX and TX DATA_END, to form transmission strobe signal Strb_Tx, is converted from parallel data to serial data at P/S circuit 123. The transmission strobe signal Strb_Tx is sent to a destination node from twisted pair A terminals TPA and TPA*. Transmission data signal Data_Tx also undergoes parallel/serial conversion at P/S circuit 124 and is transmitted to the destination node from twisted pair B terminals TPB and TPB*.
The connection of cables between the two PHY circuits is carried out as follows.
Twisted pair A terminals TPA and TPA* of a first PHY circuit connect to twisted pair B terminals TPB and TPB* of a second PHY circuit. TX_DATA_PREFIX that has been transmitted is therefore converted to data reception arbitration Rx_Data_PREFIX on the reception side, and data Data_Tx transmitted from twisted pair A terminals TPB and TPB* are received as Data_Rx by the TPA drive block on the reception side.
Received Data_Rx are converted to parallel signals by S/P circuit 125 of reception block 120 of the reception side and then synchronized to reproduced clocks and taken into FIFO 122. The data that have been taken into FIFO 122 are transmitted by way of output buffer 108 to an upper layer circuit or, in a case of selection by SEL 116, relayed to the next node.
In a case in which the PHY circuit of a node has a plurality of ports, the node can be connected to other nodes as a branch node. The node can also be connected as the parent node to other children nodes. In such a case, data are repeated by way of the bus. Data are thus transferred in a bucket brigade mode.
Packet data that are transmitted from driver 130 and driver 134 of the cable driver block are received by receivers 131 and 135 of the same port.
As can be understood from FIGS. 4 and 5, however, arbitration control signals Arb_a and Arb_b are identical for TX_DATA_PREFIX and RX_DATA_END. Bus arbitration block 119 therefore judges TX_DATA_PREFIX detected when transmitting packet data, as RX_DATA_END, and bus arbitration block 119 therefore deactivates FIFO 122. In this way, the feedback of packet data is blocked when transmitting packet data. In other words, simultaneous transmission and reception at one port is prevented.
FIG. 8 shows the relation between arbitration control signals and the output signals of bus arbitration block 119. Bus arbitration block 119 controls reception control circuit 121 in response to arbitration control signals and modifies the FIFO state.
In FIG. 8, when arbitration control signals Arb_a_TX and Arb_b_TX (“_TX” denotes “transmission”) are 0 and 1, respectively, i. e., at the time of TX_DATA_PREFIX, the FIFO state is “inactive”, and reception is thus prevented during transmission. When arbitration control signals Arb_a_TX and Arb_b_TX are 1 and 0, respectively, i. e., at the time of RX_DATA_PREFIX and TX_DATA_END, the FIFO state is “active”, and reception is thus enabled when transmission ends. This relation can also be judged in accordance with the arbitration codes of FIGS. 4 and 5.
According to FIGS. 4 and 5, arbitration control signals Arb_a=0 and Arb_b=1 correspond to TX_DATA_PREFIX as transmission arbitration code, but corresponds to RX_DATA_END as reception arbitration code.
Arbitration control signals Arb_a=1 and Arb_b=0 correspond to TX_DATA_END as transmission arbitration signal, and also correspond to RX_DATA_PREFIX as reception arbitration signal. Thus, when Arb_a=1 and Arb_b=0, the transmission circuit is deactivated, the reception circuit is activated, and the FIFO state becomes “active.”
Except in cases in which the arbitration control signals are Arb_a=1 and Arb_b=0, the FIFO state is made “inactive” and reception is disabled.
FIG. 9 shows the construction of one example of the data-strobe encoding circuit 117, and FIG. 10 shows a timing chart of data-strobe encoding.
The data-strobe encoding circuit 117 is provided with a data inversion unit and selectors 1209 and 1210.
The data inversion unit receives one-byte (from the 0 bit to the seventh bit) of parallel data signal 1207 and inverts the odd-numbered bits, i.e., the first, third, fifth, and seventh bits, at inverters 1202, 1203, 1204, and 1205.
Selector 1209 is made up by output buffer 0 for sending out strobe data that have been generated by the data inversion unit and also output buffer 1 for sending out arbitration signal 1206 that is added to the strobe data. The selection of strobe data or an arbitration signal is controlled by control signal 1208 that is provided from a transmission control circuit.
Selector 1210 is made up by output buffer 0 for sending out data signals and output buffer 1 for sending out arbitration signal 1207 that is added to the data. The selection of data signals or arbitration signals is controlled by control signal 1208 that is provided from the transmission control circuit.
FIG. 10 shows that transmission strobe signal Strb_TX is generated by inverting the first, third, fifth and seventh bits of transmission data signal Data_TX.
FIG. 10 also shows that clock signal CLK is generated from transmission strobe signal Strb_TX and transmission data signal Data_TX by Exclusive-OR gate 126 of clock reproduction circuit 128 of FIG. 7.
In addition to the normal mode for performing ordinary packet communication, communication control circuits typically operate in a test mode to test whether or not the communication control circuit is operating normally.
FIG. 11 is a block diagram for explaining one example of a test method of a communication control device for the communication control pursuant to IEEE Standard 1394.
This method is realized by performing a transmission operation and reception operation to two nodes each provided with LINK circuits and PHY circuits. This method is to be referred to as a first test method of the prior art.
In FIG. 11, the first node is provided with LINK circuit 1501 and PHY circuit 1503. The second node is provided with LINK circuit 1502 and PHY circuit 1504. External controller 1500, which is an application layer device, is connected to LINK circuit 1501 and LINK circuit 1502.
External controller 1500 is provided with test data for checking whether or not LINK circuits 1501 and 1502 and PHY circuits 1503 and 1504 are operating normally.
External controller 1500 checks whether the LINK circuits and PHY circuits are operating normally by sending the test data to one of the LINK circuits and receiving test data from the other LINK circuit and then comparing the sent test data and the received test data.
In more concrete terms, the test data from external controller 1500 is transmitted to LINK circuit 1501 and this test data are transmitted to PHY circuit 1503. PHY circuit 1503, when receiving the test data, transmits the test data to IEEE 1394 cable 1505.
PHY circuit 1504 receives the test data by way of IEEE 1394 cable 1505 and transmits the test data to LINK circuit 1502.
Having received the test data, LINK circuit 1502 transmits the test data to external controller 1500.
Testing LINK circuits and PHY circuits according to the first test method of the prior art therefore not only requires that test data be transmitted to LINK circuits and PHY circuits, but further requires an external controller for receiving test data that have been processed by the LINK circuits and PHY circuits. This method of the prior art is therefore problematic due to its complexity.
A testing method that improves on the first method of the prior art to meet the demand for a simplified test is described in, for example, Japanese Patent Laid-open No. 4240/99.
In this method, an external controller that supplies test data is provided inside an LSI as a test circuit. This method is described below as a second test method of the prior art.
FIG. 12 is a block diagram of a communication control device for the second test method of the prior art.
The communication control circuits that are the objects of testing are an LSI that includes LINK circuit 1601 and PHY circuit 1603 and an LSI that includes LINK circuit 1602 and PHY circuit 1604. The external controller is incorporated as test circuit 1600 in at least one of the LINK circuits. During testing, PHY circuits 1603 and 1604 are connected by cable 1605 and test circuit 1600 carries out the transmission and reception of test signals by control from outside the LINK circuits.
During a test, test data are transmitted from a test circuit inside one of the LINK circuits, and the test data that have been transmitted by way of a PHY circuit, a cable, a PHY circuit, and a LINK circuit are compared with the original test data supplied from the test circuit 1600 at an external logic analyzer circuit.
As the cable, a cable is used that conforms with IEEE Standard 1394 used in normal operation.
The use of this cable, however, causes the problem that tests on each of the LSI are more difficult, and there has consequently been demand for operation tests that are performed on each LSI.
A semiconductor device that meets this demand is described in, for example, Japanese Patent Laid-open No. 170606/98. Wiring and switches that take the place of a cable are provided within an LSI. This method is referred to hereinbelow as the third test method of the prior art.
FIG. 13 is a circuit diagram of an LSI for realizing a third method of the prior art.
This LSI incorporates first port PRT1 and second port PRT2. First port PRT1 is provided with input/output terminal T1, driver (DRV1) 1711 for transmitting data signal TXD1 from terminal T1, and receiver (RCV1) 1712 for receiving data signal RXD1 from terminal T1. Driver 1711 is controlled by transmission control signal TXE1, and receiver 1712 is controlled by reception control signal RXE1.
Second port PRT2 is also provided with input/output terminal T2, driver (DRV2) 1713 for transmitting data signal TXD2 from terminal T2, and receiver (RCV2) 1714 for receiving data signal RXD2 from terminal T2. Driver 1713 is controlled by transmission control signal TXE2, and receiver 1714 is controlled by reception control signal RXE2.
Switch (on-resistance=Rsw) 1710 is provided between first port PRT 1 and second port PRT2 for switching between connection/disconnection of these two ports, the connection of switch 1710 being controlled by control signal CNT. Termination resistors 1701 and 1702 of resistance R0 are connected to terminals T1 and T2.
When testing, a loopback test can be performed by connecting switch 1710, whereby a test can be performed on the LSI.
However, since wiring and switches are provided between the ports, this test circuit has the problem that the parasitic capacitance of the wiring and switches obstructs high-speed operation during normal operation.
Although it is possible to use an LSI tester capable of high-speed operation to perform a test on an LSI at a high speed equivalent to normal speed, such LSI testers that operate at high speed are expensive.
It is an object of the present invention to provide a communication control circuit that can easily perform an operation test of a communication control circuit that includes a PHY circuit on a low-speed LSI and at a high speed equivalent to normal operation.